This invention relates in general to printed circuit boards and in particular to printed circuit boards adapted to mount and connect a plurality of semiconductor devices. Still more particularly, this invention relates to multiplane printed circuit boards including means for minimizing parasitic capacitance.
Printed circuit boards are well known in the prior art. More specifically, certain printed circuit boards are designed to permit so-called "breadboarding" of electronic circuits to determine the feasibility of a proposed circuit layout or design prior to committing to production boards.
A conventional prior art breadboard typically consists of a flat insulating substrate which is perforated at regular intervals so as to permit insertion of electrical and electronic components and jumper wires, so that electronic circuits may be laid out and tested. Many methods exist for electrically coupling individual components together including: soldering, wire wrapping, stitch wiring and quick connects. Preferably, a printed circuit board utilized for breadboarding will permit one or more of the preceding techniques to be utilized.
One example of a prior art printed circuit board which may be utilized for breadboarding electronic circuits may be seen in U.S. Pat. No. 4,330,684 issued to Hayward. The Hayward patent discloses a printed circuit board which includes multiple bus elements plated onto the board to permit interconnection of the circuit elements to selected and common electrical points, (e.g. electrical power and ground).
Another prior art printed circuit board is disclosed in U.S. Pat. No. 3,217,208 issued to Castro. The Castro printed circuit board discloses the technique of providing apertures which permit the electrical conductors to be inserted from below to make an electrical connection with components mounted on the upper surface of the board.
Those skilled in the art will appreciate that two problems exist with known printed circuit boards. One problem involves the effective utilization of space so that a maximum number of circuit elements may be mounted onto a board of a given area. Another problem involves the minimization of possible parasitic capacitance which sometimes exists in multiplane boards.
Thus, it should be apparent that a need exists for a printed circuit board for mounting and connecting a plurality of semiconductor devices that permits maximum utilization of board space while minimizing parasitic capacitance.